About Neuralink:
We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.
Team Description:
The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.
Job Description and Responsibilities:
We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems. You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As an Analog IC Layout Engineer, your responsibilities will include:
Required Qualifications:
Preferred Qualifications:
Expected Compensation:
The anticipated base salary for this position is expected to be within the following range. Your actual base pay will be determined by your job-related skills, experience, and relevant education or training. We also believe in aligning our employees’ success with the company's long-term growth. As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees.
What We Offer:
Full-time employees are eligible for the following benefits listed below.
Will AI replace this role?
Check AI displacement risk, transferable skills, and career alternatives for Analog IC Layout Engineer
The salary range for the Analog IC Layout Engineer position at Neuralink is USD 83k+/yr.
The Analog IC Layout Engineer position at Neuralink is based in South San Francisco, California, United States; Fremont, California, United States. This is an on-site position.
The Analog IC Layout Engineer position at Neuralink is a Full time role.
The Analog IC Layout Engineer position at Neuralink requires 2+ yrs exp.
Key skills for the Analog IC Layout Engineer position at Neuralink include: c++, python.
