Hire(d) better.
Hire(d) better.
Hire(d) better.
OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform.
We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale.
This is a senior, hands-on engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure, physical design convergence, bring-up, and production readiness. You will plan and oversee the work of junior engineers and help drive and develop productive engineering relationships with external partners and help manage partner execution.
This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.
Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic-management logic as well as off-chip protocol bridges and interfaces.
Drive third party engagements to develop novel networking and interface protocols and silicon IP while ensuring high quality and design integrity, leveraging deep technical and non-technical leadership skills.
Perform substantial direct microarchitecture and RTL coding work.
Collaborate with architecture and design team members on the overall solution and execution plan for cutting-edge large-scale custom silicon.
Work with performance and architecture teams to analyze traffic patterns, identify bottlenecks, and optimize interconnect behavior under realistic system workloads.
Collaborate with design verification teams to develop verification strategies, coverage plans, assertions, stress scenarios, and debug approaches for highly concurrent fabric behavior.
Partner with physical design teams to ensure interconnect structures are implementable at target frequency, power, and area, including floorplan-aware design, pipeline strategy, timing closure, and congestion management.
Provide technical leadership through design reviews, architecture reviews, documentation, mentoring, and development of reusable RTL and integration methodologies.
Leverage experience to help raise the bar on design work inside our team.
Roll up your sleeves and get your hands dirty!
Extensive industry experience designing and delivering complex SoC interconnect, NoC, coherent fabric, memory subsystem, cache-coherent, or chip-level integration solutions.
A strong track record of owning major RTL blocks or SoC subsystems from microarchitecture through tape-out and silicon bring-up.
Deep expertise in Verilog/SystemVerilog and the development of clean, parameterized, production-quality RTL.
Strong understanding of interconnect concepts such as topology, routing, arbitration, virtual channels, flow control, buffering, ordering, quality of service, coherency, deadlock avoidance, congestion management, and performance monitoring.
Experience with common on-chip or chip-to-chip protocols and interfaces, such as AXI, APB, CXL, PCIe, Ethernet.
Experience building custom networking protocols or protocol extensions.
Experience working designing and implementing subsystems in the context of large scale systems built with RDMA/RoCE or other HPC-style system-level interconnects.
Familiarity and deep experience with the full spectrum of industry-standard RTL-adjacent development and signoff flows, including lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, and design-for-test considerations.
Experience working closely with architecture, verification, physical design, firmware, performance, and post-silicon teams to deliver complex silicon.
Strong judgment in making practical design tradeoffs across performance, power, area, schedule, verification risk, and physical implementation constraints.
Excellent communication skills and the ability to provide technical direction, mentor engineers, and drive alignment across multiple teams.
Passion for achieving high leverage through complexity reduction, automation and creative pragmatism.
Experience designing interconnect for AI accelerators, GPUs, CPUs, high-performance computing systems, networking silicon, or large-scale datacenter silicon.
Experience with memory consistency, virtualization, isolation, RAS, telemetry, or security requirements within complex SoCs.
Experience with NoC performance modeling, traffic simulation, emulation, FPGA prototyping, or post-silicon performance analysis.
Experience leading architecture or RTL delivery for first-generation silicon programs or rapidly evolving hardware platforms.
To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.
About OpenAI
OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.
We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic.
For additional information, please see OpenAI’s Affirmative Action and Equal Employment Opportunity Policy Statement.
Background checks for applicants will be administered in accordance with applicable law, and qualified applicants with arrest or conviction records will be considered for employment consistent with those laws, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act, for US-based candidates. For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. In addition, job duties require access to secure and protected information technology systems and related data security obligations.
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We are committed to providing reasonable accommodations to applicants with disabilities, and requests can be made via this link.
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At OpenAI, we believe artificial intelligence has the potential to help people solve immense global challenges, and we want the upside of AI to be widely shared. Join us in shaping the future of technology.
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Check AI displacement risk, transferable skills, and career alternatives for Senior RTL Engineer, Interconnect Design
The Senior RTL Engineer, Interconnect Design position at Openai is based in San Francisco. This is a hybrid position.
The Senior RTL Engineer, Interconnect Design position at Openai is a Full time role.
Key skills for the Senior RTL Engineer, Interconnect Design position at Openai include: ai.
